An integrated circuit may be composed of a plurality of semiconductor devices, such as transistors or the like, which can be produced by a variety of techniques. To facilitate increased integration and speed of semiconductor devices, a geometrical progression of continuously scaling semiconductor devices (e.g., decreasing transistor size, increasing transistor areal density, etc.) has emerged. Reducing the size of a semiconductor device and/or a feature size of a semiconductor device can provide improved speed, performance, density, cost per unit, etc., of resultant integrated circuits. However, as the size of semiconductor devices and device features have been reduced, conventional fabrication techniques (e.g., lithography) are being challenged in their ability to produce modules comprising a plurality of integrated circuits located with high proximity to each other. For example, fin-field effect transistors (fin-FET) are being manufactured with a 22 nanometer gate, which is a few 10s of atoms across. Hence, the limits of lateral scaling of devices, and their manufacture, are being reached. Accordingly, the Semiconductor Industry Association has recognized the limits of conventional planar manufacture of semiconductor devices and accordingly has identified three dimensional-integrated circuit (3D-IC) fabrication as a core enabler in keeping pace with Moore's Law.
For example, while a fin-FET is topographically a 3D structure, conventional manufacture of a fin-FET is by way of a standard planar process flow. However, it is not possible to extend the planar process flow repetitively in the vertical dimension to capture 3D volumetric scaling of transistor density, and construction of a 3D structure is severely hampered when limited to 2D viewing and processing.
It could be opined that current CMOS having 7-10 layers of metallization are 3D, however these structures can be viewed as the result of a succession of strictly 2D operations. In addition, the phrase 3D-IC is used in the semiconductor industry and literature to describe a subset of devices typically formed by stacking successive functional 2D planar die, and making use of through-wafer vias (or through-silicon vias), or by bonding die in a face-to-face manner. In both forms, the plane containing the transistors and interconnects for each level is parallel to the wafer surface.
Hence, to enable 3D-IC fabrication, where the functional semiconductor devices are fabricated on surfaces which are not parallel to the wafer surface, to be realized, new approaches to semiconductor device manufacture have to be engendered. 3D fabrication is an approach to extending effective areal density, but current methods (e.g., nano-origami, direct laser write, etc.) of 3D fabrication at the sub-micron scale are rare, typically not CMOS-compatible, require non-standard equipment, and lack high-volume manufacturing scalability.